| | Top Stories — April 02, 2015 | | | Deeper Dive: Xpedition Enables Co-Design of Chips, Packages, Boards
A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first. | | MicroWatt Chips shown at ISSCC
With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). | | Proponents of EUV, immersion lithography face off at SPIE
The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium. EUVt lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML's EUV customers, notably Intel, Samsung Electronics, and TSMC. On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers. | | Directed Self Assembly Hot Topic at SPIE
At this week's SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly. | | Complexity is the Theme at Lithography Conference
Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes. | | Learning to live with negative tone
In lithography for manufacturing semiconductors, a negative tone can be a positive attribute. | | SPIE Advanced Lithography conference concludes
Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley. | | more top stories  |
| News & Features | | | Solid State Technology's Latest Issue
The March issue of SST features articles on a new supplier hub, advanced analytics for yield improvement and zero defect in semiconductors, acoustic inspection of packages, chip-package co-design, techniques for simplifying pulsed measurements, and web tension control in roll-to-roll web processing. | | Time to "shift left" in chip design and verification, Synopsys founder says
Taking "Smart Design from Silicon to Software" as his official theme, Aart de Geus urged attendees to "shift left" – in other words, "squeezing the schedule" to design, verify, debug, and manufacture semiconductors. | | | more news & features |
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| | | | Our Sponsors | | | | | | Videos/Podcasts | | | | Solid State Watch: March 6-12, 2015 | |  | | | Cypress and Spansion complete merger; Strong fab equipment spending forecast for 2015; 11 IC product categories to exceed total IC market growth in 2015; Global mobile phone display module shipments signal stronger competition among manufacturers | | | More Videos/Podcasts | | | White Papers | | | | RF-SOI Wafers for Wireless Applications | | The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance. | | | DFM: What is it and what will it do? | | Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda. | | | Via Doubling to Improve Yield | | In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area. | | | The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions | | Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters. | | | A Study Of Model-Based Etch Bias Retarget For OPC | | The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension. | | | | more white papers |
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